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FSTD16211 24-Bit Bus Switch with Level Shifting
June 2000 Revised June 2000
FSTD16211 24-Bit Bus Switch with Level Shifting
General Description
The Fairchild Switch FSTD16211 provides 24-bits of highspeed CMOS TTL-compatible bus switching. The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. A diode to VCC has been integrated into the circuit to allow for level shifting between 5V inputs and 3.3V outputs. The device is organized as a 12-bit or 24-bit bus switch. When OE1 is LOW, the switch is ON and Port 1A is connected to Port 1B. When OE2 is LOW, Port 2A is connected to Port 2B. When OE1/2 is HIGH, a high impedance state exists between the A and B Ports.
Features
s 4 switch connection between two ports. s Minimal propagation delay through the switch. s Low lCC. s Zero bounce in flow-through mode. s Control inputs compatible with TTL level.
Ordering Code:
Order Number FSTD16211MTD Package Number MTD56 Package Description 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Logic Diagram
Connection Diagram
Truth Table
Inputs OE1 L L H H OE2 L H L H Inputs/Outputs 1A, 1B 1A = 1B 1A = 1B Z Z 2A, 2B 2A = 2B Z 2A = 2B Z
Pin Descriptions
Pin Name OE1, OE2 1A, 2A 1B, 2B Description Bus Switch Enables Bus A Bus B
(c) 2000 Fairchild Semiconductor Corporation
DS500313
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FSTD16211
Absolute Maximum Ratings(Note 1)
Supply Voltage (VCC) DC Switch Voltage (VS) (Note 2) DC Input Control Pin Voltage (VIN)(Note 3) DC Input Diode Current (lIK) VIN < 0V DC Output (IOUT) DC VCC/GND Current (ICC/IGND) Storage Temperature Range (TSTG)
-0.5V to +7.0V -0.5V to +7.0V -0.5V to +7.0V -50mA
128mA
Recommended Operating Conditions (Note 4)
Power Supply Operating (VCC) Input Voltage (VIN) Output Voltage (VOUT) Input Rise and Fall Time (tr, tf) Switch Control Input Switch I/O Free Air Operating Temperature (TA) 0nS/V to 5nS/V 0nS/V to DC -40 C to +85 C 4.5V to 5.5V 0V to 5.5V 0V to 5.5V
+/- 100mA -65C to +150 C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum rating. The "Recommended Operating Conditions" table will define the conditions for actual device operation. Note 2: VS is the voltage observed/applied at either A or B Ports across the switch. Note 3: The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. Note 4: Unused control inputs must be held HIGH or LOW. They may not float.
DC Electrical Characteristics
VCC Symbol VIK VIH VIL VOH II IOZ RON Parameter Clamp Diode Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Input Leakage Current OFF-STATE Leakage Current Switch On Resistance (Note 6) ICC Quiescent Supply Current (V) 4.5 4.5-5.5 4.5-5.5 4.5-5.5 5.5 0 5.5 4.5 4.5 4.5 5.5 4 4 35 See Figure 3 1.0 10 1.0 7 7 50 1.5 10 ICC Increase in ICC per Input 5.5 2.5 2.0 0.8 TA = -40 C to +85 C Min Typ (Note 5) Max -1.2 Units V V V V A A A mA A mA 0 VIN 5.5V VIN = 5.5V 0 A, B VCC VIN = 0V, IIN = 64mA VIN = 0V, IIN = 30mA VIN = 2.4V, IIN = 15mA OE1 = OE2 = GND VIN = VCC or GND, IOUT = 0 OE1 = OE2 = V CC VIN = VCC or GND, IOUT = 0 One input at 3.4V Other inputs at VCC or GND
Note 5: Typical values are at VCC = 5.0V and T A= +25C Note 6: Measured by the voltage drop between A and B pins at the indicated current through the switch. On resistance is determined by the lower of the voltages on the two (A or B) pins.
Conditions IIN = -18mA
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FSTD16211
AC Electrical Characteristics
TA = -40 C to +85 C, Symbol Parameter CL = 50pF, RU = RD = 500 VCC = 4.5 - 5.5V Min tPHL,tPLH tPZH, tPZL tPHZ, tPLZ Prop Delay Bus to Bus (Note 7) Output Enable Time Output Disable Time 1.5 1.5 Max 0.25 5.5 6.5 ns ns ns VI = OPEN VI = 7V for tPZL VI = OPEN for tPZH VI = 7V for tPLZ VI = OPEN for tPHZ Figures 1, 2 Figures 1, 2 Figures 1, 2 Units Conditions Figure Number
Note 7: This parameter is guaranteed by design but is not tested. The bus switch contributes no propagation delay other than the RC delay of the typical ON resistance of the switch and the 50pF load capacitance, when driven by an ideal voltage source (zero output impedance).
Capacitance
Symbol CIN CI/O
(Note 8)
Parameter Typ 3.5 5.5 Max Units pF pF Conditions VCC = 5.0V VCC, OE = 5.0V
Control Pin Input Capacitance Input/Output Capacitance
Note 8: TA = +25C, f = 1 MHz, Capacitance is characterized but not tested.
AC Loading and Waveforms
Note: Input driven by 50 source terminated in 50 Note: CL includes load and stray capacitance Note: Input PRR = 1.0 MHz, tW = 500 ns
FIGURE 1. AC Test Circuit
FIGURE 2. AC Waveforms
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FSTD16211
Output Voltage HIGH vs. Supply Voltage
FIGURE 3. www.fairchildsemi.com 4
FSTD16211 24-Bit Bus Switch with Level Shifting
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
Technology Description
The Fairchild Switch family derives from and embodies Fairchild's proven switch technology used for several years in its 74LVX3L384 (FST3384) bus switch product.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 5 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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